High Level Design (Altera/Xilinx)
For more information contact:
Leading specialistOrdynskaya Marina Yurievna, room 607-7., tel. +375 17 397-82-95, +375 29 639-65-63,
e-mail:ordinskaya@bsuir.by
leading specialistKrischenovich Veronika Anatolyevna,room 607-7., tel. +375 17 397-82-95, +375 29 390-88-95,
e-mail:krish@bsuir.by
Deputy DeanGarbuz Vitaly Borisovich, room 402-8., tel. +375 29 686-61-14,
e-mail:garbuz@bsuir.by
Registration is carried out via an electronic form. Training begins as groups are formed.
Price
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Duration
72 hours
About the program
Course program
High-level synthesis packages Qsys, Quartus II/Vivado.
Languages SystemVerilog, OpenCL/SystemC, extended C/C++.
Definition of system functions.
Definition of parallel processes.
Conveyor design.
System memory design.
Synchronization design.
I/O design.
Dividing the system into software and hardware parts.
High-level modeling.
Obtaining hardware descriptions in Verilog/VHDL languages.
Optimization of area, performance, energy consumption.
Apply for the program
High Level Design (Altera/Xilinx)