High-level design of digital systems based on the SystemVerilog language
For more information contact:
Leading specialistOrdynskaya Marina Yurievna, room 607-7., tel. +375 17 397-82-95, +375 29 639-65-63,
e-mail:ordinskaya@bsuir.by
leading specialistKrischenovich Veronika Anatolyevna,room 607-7., tel. +375 17 397-82-95, +375 29 390-88-95,
e-mail:krish@bsuir.by
Deputy DeanGarbuz Vitaly Borisovich, room 402-8., tel. +375 29 686-61-14,
e-mail:garbuz@bsuir.by
Registration is carried out via an electronic form. Training begins as groups are formed.
Price
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Duration
72 hours
About the program
Course program
Basics of the SystemVerilog language. General overview.
Literal meanings. Data types.
Arrays. Data declarations. Classes. Operations and expressions.
Planning semantics: execution of the hardware model and its verification framework, event modeling, event scheduler, callback checkpoints.
Procedural statements and flow control.
Processes.
Tasks and functions.
Random restrictions.
Interprocess synchronization and communication.
Block synchronization.
Program block. Statements.
Coatings. Hierarchy. Interfaces.
Configuration libraries. System tasks and functions. Compiler directives. Dump value changes.
Direct programming of interfaces. Object model. Modeling finite state machines.
Design of hierarchical structures.
Simulation of a completed project.
Modeling at the behavioral level.
Simulation at the gear level.
Apply for the program
High-level design of digital systems based on the SystemVerilog language